关于连续电压集成电路的另一个注意事项是，由于该系列的三态功能，禁用电流被保持到最小。当三态引脚拉低时，石英晶体振荡器和CMOS输出缓冲器停止工作。正如IC拓扑结构(图2)所示，输出缓冲区被拉到VDD。禁用电流是由内部的上拉电阻决定的，它允许在指定的电源范围内从源拉出不超过10μA。

Abracon晶振编码ASA-16.000MHZ-L-T，SMD晶振，有源晶振超迷你包装,2.0 x 1.6 x 0.7mm，三态函数，适合高密度SMT，符合RoHS标准回流过程，接缝密封包装保证，高可靠性，应用：录像机CCD时钟，计算机和外围设备，便携式电子设备，移动通信，PDA。

The combination of a fundamental mode IC topology, a 3rd overtone IC topology and an internal divider chain allows for the Continuous Voltage oscillator family to reach a broad frequency range of 1 to 160MHz.

Another note to consider with respect to the Continuous Voltage ICs is that the disable current is kept to a minimum thanks to the family’s tri-state functionality. When the tri-state pin is pulled low, the oscillator and CMOS output buffer cease operation. As seen in the IC topologies (Fig. 2), the output buffer is pulled up to VDD. The disable current is dictated by the internal pull-up resistor, which allows no more than 10μA draw from the source over the specified supply range.
The typical frequency deviation is well within ±1ppm across the offered frequency range, which satisfies the requirements of most battery-powered applications. Keeping the current consumption to a minimum is also a priority across the Continuous Voltage oscillator family.